Acquisition Performance of a Digital Phase Locked Loop with a Four-Quadrant Arctan Phase Detector

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dc.contributor.author Sithamparanathan, K
dc.contributor.author Reisenfeld, S
dc.contributor.editor NA
dc.date.accessioned 2009-11-09T05:37:56Z
dc.date.issued 2004-01
dc.identifier.citation ISPACS 2004 Proceedings, 2004, pp. 1 - 5
dc.identifier.isbn 0-7803-8640-X
dc.identifier.other E1 en_US
dc.identifier.uri http://hdl.handle.net/10453/3028
dc.description.abstract The acquisition performance of a digital phase locked loop (DPLL) with a four-quadrant arctan based phase detector (PD) is discussed. In the noiseless case, unlike the traditional sine function based phase locked loops, the acquisition process of the four-quadrant arctan based phase locked loops is less tedious. We look into the pull-in process together with a time-series analysis of the DPLL for the noiseless case. The phase-plane portrait of the loop is also discussed, for both the noiseless and the noisy conditions.
dc.publisher ISPACS Committee
dc.relation.isbasedon 10.1109/ISPACS.2004.1439139
dc.title Acquisition Performance of a Digital Phase Locked Loop with a Four-Quadrant Arctan Phase Detector
dc.type Conference Proceeding
dc.parent ISPACS 2004 Proceedings
dc.journal.number en_US
dc.publocation Seoul, Korea en_US
dc.identifier.startpage 1 en_US
dc.identifier.endpage 5 en_US
dc.cauo.name FEIT.School of Elec, Mech and Mechatronic Systems en_US
dc.conference Verified OK en_US
dc.conference International Symposium on Intelligent Signal Processing and Communications Systems
dc.conference.location Seoul, Korea en_US
dc.for 0906 Electrical and Electronic Engineering
dc.personcode 880567
dc.percentage 100 en_US
dc.classification.name Electrical and Electronic Engineering en_US
dc.classification.type FOR-08 en_US
dc.custom International Symposium on Intelligent Signal Processing and Communications Systems en_US
dc.date.activity 20041118 en_US
dc.date.activity 2004-11-18
dc.location.activity Seoul, Korea en_US
dc.description.keywords digital phase locked loops phase detectors phase noise en_US
dc.description.keywords digital phase locked loops phase detectors phase noise
pubs.embargo.period Not known
pubs.organisational-group /University of Technology Sydney
pubs.organisational-group /University of Technology Sydney/Faculty of Engineering and Information Technology
pubs.organisational-group /University of Technology Sydney/Faculty of Engineering and Information Technology/School of Computing and Communications
utslib.copyright.status Closed Access
utslib.copyright.date 2015-04-15 12:23:47.074767+10
utslib.collection.history General (ID: 2)


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