Magnetically isolated gate driver with leakage inductance immunity

Muhammad, KS; Lu, DDC

Magnetically isolated gate driver with leakage inductance immunity

Muhammad, KS Lu, DDC

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Publication Type:: Journal Article
Citation:: IEEE Transactions on Power Electronics, 2014, 29 (4), pp. 1567 - 1572
Issue Date:: 2014-01-01

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Field	Value	Language
dc.contributor.author	Muhammad, KS	en_US
dc.contributor.author	Lu, DDC https://orcid.org/0000-0003-2145-0580	en_US
dc.date.issued	2014-01-01	en_US
dc.identifier.citation	IEEE Transactions on Power Electronics, 2014, 29 (4), pp. 1567 - 1572	en_US
dc.identifier.issn	0885-8993	en_US
dc.identifier.uri	http://hdl.handle.net/10453/118653
dc.description.abstract	This letter presents the design of a magnetically isolated gate driver with high immunity to leakage inductance. The proposed gate driver (PGD) is developed based on a bipolar totempole gate driver (noninverting) located on the secondary side of the coupling transformer. It is able to drive a MOSFET/IGBT from standard CMOS to TTL output and down to LSTTL level. It also achieves large duty cycle ratio and small input to output delay and provides reliable isolation. In this letter, the PGD is analyzed and verified experimentally. The design guidelines are also provided including design considerations. © 1986-2012 IEEE.	en_US
dc.relation.ispartof	IEEE Transactions on Power Electronics	en_US
dc.relation.isbasedon	10.1109/TPEL.2013.2279548	en_US
dc.rights	info:eu-repo/semantics/closedAccess
dc.subject.classification	Electrical & Electronic Engineering	en_US
dc.title	Magnetically isolated gate driver with leakage inductance immunity	en_US
dc.type	Journal Article
utslib.citation.volume	4	en_US
utslib.citation.volume	29	en_US
utslib.for	0906 Electrical and Electronic Engineering	en_US
pubs.embargo.period	Not known	en_US
pubs.organisational-group	/University of Technology Sydney
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology/School of Electrical and Data Engineering
utslib.copyright.status	closed_access	*
pubs.issue	4	en_US
pubs.publication-status	Published	en_US
pubs.volume	29	en_US

Abstract:

This letter presents the design of a magnetically isolated gate driver with high immunity to leakage inductance. The proposed gate driver (PGD) is developed based on a bipolar totempole gate driver (noninverting) located on the secondary side of the coupling transformer. It is able to drive a MOSFET/IGBT from standard CMOS to TTL output and down to LSTTL level. It also achieves large duty cycle ratio and small input to output delay and provides reliable isolation. In this letter, the PGD is analyzed and verified experimentally. The design guidelines are also provided including design considerations. © 1986-2012 IEEE.

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http://hdl.handle.net/10453/118653