Two-transistor step-down DC/DC converters with fault-tolerant capability

Dah-Chuan Lu, D; Soon, JL; Verstraete, D

Two-transistor step-down DC/DC converters with fault-tolerant capability

Dah-Chuan Lu, D

Soon, JL Verstraete, D

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Publication Type:: Conference Proceeding
Citation:: 2014 Australasian Universities Power Engineering Conference, AUPEC 2014 - Proceedings, 2014
Issue Date:: 2014-01-01

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Field	Value	Language
dc.contributor.author	Dah-Chuan Lu, D https://orcid.org/0000-0003-2145-0580	en_US
dc.contributor.author	Soon, JL	en_US
dc.contributor.author	Verstraete, D	en_US
dc.date.issued	2014-01-01	en_US
dc.identifier.citation	2014 Australasian Universities Power Engineering Conference, AUPEC 2014 - Proceedings, 2014	en_US
dc.identifier.isbn	9780646923758	en_US
dc.identifier.uri	http://hdl.handle.net/10453/121128
dc.description.abstract	© 2014 ACPE. This paper presents a family of two-transistor step-down dc/dc converters with fault-tolerant capability which is derived through graph theoretic approach. The fault-tolerant property deals with open-circuit fault of one of the power transistors in a two-transistor dc/dc converter structure. Under normal operation, either one of the two transistors can be used to control the power flow and the other transistor is idle. When the fault occurs, the other transistor will be activated to provide an alternate current path to continue converter operation and maintain output regulation. Derivation procedure and some experimental results are reported.	en_US
dc.relation.ispartof	2014 Australasian Universities Power Engineering Conference, AUPEC 2014 - Proceedings	en_US
dc.relation.isbasedon	10.1109/AUPEC.2014.6966574	en_US
dc.rights	info:eu-repo/semantics/closedAccess
dc.title	Two-transistor step-down DC/DC converters with fault-tolerant capability	en_US
dc.type	Conference Proceeding
utslib.for	0906 Electrical and Electronic Engineering	en_US
pubs.embargo.period	Not known	en_US
pubs.organisational-group	/University of Technology Sydney
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology/School of Electrical and Data Engineering
utslib.copyright.status	closed_access	*
pubs.publication-status	Published	en_US

Abstract:

© 2014 ACPE. This paper presents a family of two-transistor step-down dc/dc converters with fault-tolerant capability which is derived through graph theoretic approach. The fault-tolerant property deals with open-circuit fault of one of the power transistors in a two-transistor dc/dc converter structure. Under normal operation, either one of the two transistors can be used to control the power flow and the other transistor is idle. When the fault occurs, the other transistor will be activated to provide an alternate current path to continue converter operation and maintain output regulation. Derivation procedure and some experimental results are reported.

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http://hdl.handle.net/10453/121128