Specification format and a verification method of fault-tolerant quantum circuits

Paler, A; Devitt, SJ

Specification format and a verification method of fault-tolerant quantum circuits

Paler, A Devitt, SJ

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Publication Type:: Journal Article
Citation:: Physical Review A, 2018, 98 (2)
Issue Date:: 2018-08-02

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Field	Value	Language
dc.contributor.author	Paler, A	en_US
dc.contributor.author	Devitt, SJ https://orcid.org/0000-0002-5901-1391	en_US
dc.date.issued	2018-08-02	en_US
dc.identifier.citation	Physical Review A, 2018, 98 (2)	en_US
dc.identifier.issn	2469-9926	en_US
dc.identifier.uri	http://hdl.handle.net/10453/127218
dc.description.abstract	© 2018 American Physical Society. Quantum computations are expressed in general as quantum circuits, which are specified by ordered lists of quantum gates. The resulting specifications are used during the optimization and execution of the expressed computations. However, the specification format makes it difficult to verify that optimized or executed computations still conform to the initial gate list specifications: showing the computational equivalence between two quantum circuits expressed by different lists of quantum gates is exponentially complex in the worst case. In order to solve this issue, this work presents a derivation of the specification format tailored specifically for fault-tolerant quantum circuits. The circuits are considered a form consisting entirely of single qubit initializations, cnot gates, and single qubit measurements (ICM form). This format allows, under certain assumptions, to efficiently verify optimized (or implemented) computations. Two verification methods based on checking stabilizer circuit structures are presented.	en_US
dc.relation.ispartof	Physical Review A	en_US
dc.relation.isbasedon	10.1103/PhysRevA.98.022302	en_US
dc.subject.classification	General Physics	en_US
dc.title	Specification format and a verification method of fault-tolerant quantum circuits	en_US
dc.type	Journal Article
utslib.citation.volume	2	en_US
utslib.citation.volume	98	en_US
utslib.for	0803 Computer Software	en_US
utslib.for	01 Mathematical Sciences	en_US
utslib.for	02 Physical Sciences	en_US
utslib.for	03 Chemical Sciences	en_US
pubs.embargo.period	Not known	en_US
pubs.organisational-group	/University of Technology Sydney
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology
pubs.organisational-group	/University of Technology Sydney/Strength - QSI - Centre for Quantum Software and Information
utslib.copyright.status	open_access
pubs.issue	2	en_US
pubs.publication-status	Published	en_US
pubs.volume	98	en_US

Abstract:

© 2018 American Physical Society. Quantum computations are expressed in general as quantum circuits, which are specified by ordered lists of quantum gates. The resulting specifications are used during the optimization and execution of the expressed computations. However, the specification format makes it difficult to verify that optimized or executed computations still conform to the initial gate list specifications: showing the computational equivalence between two quantum circuits expressed by different lists of quantum gates is exponentially complex in the worst case. In order to solve this issue, this work presents a derivation of the specification format tailored specifically for fault-tolerant quantum circuits. The circuits are considered a form consisting entirely of single qubit initializations, cnot gates, and single qubit measurements (ICM form). This format allows, under certain assumptions, to efficiently verify optimized (or implemented) computations. Two verification methods based on checking stabilizer circuit structures are presented.

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http://hdl.handle.net/10453/127218