A DC-Reactor-Based Solid-State Fault Current Limiter for HVdc Applications

Heidary, A; Radmanesh, H; Rouzbehi, K; Pou, J

A DC-Reactor-Based Solid-State Fault Current Limiter for HVdc Applications

Heidary, A Radmanesh, H Rouzbehi, K

Pou, J

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Publication Type:: Journal Article
Citation:: IEEE Transactions on Power Delivery, 2019, 34 (2), pp. 720 - 728
Issue Date:: 2019-04-01

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Field	Value	Language
dc.contributor.author	Heidary, A	en_US
dc.contributor.author	Radmanesh, H	en_US
dc.contributor.author	Rouzbehi, K https://orcid.org/0000-0002-3623-4840	en_US
dc.contributor.author	Pou, J	en_US
dc.date.issued	2019-04-01	en_US
dc.identifier.citation	IEEE Transactions on Power Delivery, 2019, 34 (2), pp. 720 - 728	en_US
dc.identifier.issn	0885-8977	en_US
dc.identifier.uri	http://hdl.handle.net/10453/134761
dc.description.abstract	© 1986-2012 IEEE. Expansion of high-voltage dc (HVdc) systems to multi-terminal HVdc (MT-HVdc) systems/grids considerably increases the short-circuit levels. In order to protect the emerging MT-HVdc systems/grids against fault currents, proper dc fault current limiters (FCLs) must be developed. This paper proposes an innovative high inductance solid-state dc-reactor-based FCL (HISS-DCRFCL) to be used in HVdc applications. In fact, during the HISS-DCRFCL normal operation, its inductance value is extremely low, and its value becomes considerably high during the fault period, which decreases the fault current amplitude. The proposed HISS-DCRFCL performance is analyzed by MATLAB/Simulink and the simulation results are verified and confirmed by laboratory experimental results using a scaled-down laboratory prototype setup.	en_US
dc.relation.ispartof	IEEE Transactions on Power Delivery	en_US
dc.relation.isbasedon	10.1109/TPWRD.2019.2894521	en_US
dc.rights	info:eu-repo/semantics/closedAccess
dc.subject.classification	Energy	en_US
dc.title	A DC-Reactor-Based Solid-State Fault Current Limiter for HVdc Applications	en_US
dc.type	Journal Article
utslib.citation.volume	2	en_US
utslib.citation.volume	34	en_US
utslib.for	0906 Electrical and Electronic Engineering	en_US
pubs.embargo.period	Not known	en_US
pubs.organisational-group	/University of Technology Sydney
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology/School of Electrical and Data Engineering
utslib.copyright.status	closed_access	*
pubs.issue	2	en_US
pubs.publication-status	Published	en_US
pubs.volume	34	en_US

Abstract:

© 1986-2012 IEEE. Expansion of high-voltage dc (HVdc) systems to multi-terminal HVdc (MT-HVdc) systems/grids considerably increases the short-circuit levels. In order to protect the emerging MT-HVdc systems/grids against fault currents, proper dc fault current limiters (FCLs) must be developed. This paper proposes an innovative high inductance solid-state dc-reactor-based FCL (HISS-DCRFCL) to be used in HVdc applications. In fact, during the HISS-DCRFCL normal operation, its inductance value is extremely low, and its value becomes considerably high during the fault period, which decreases the fault current amplitude. The proposed HISS-DCRFCL performance is analyzed by MATLAB/Simulink and the simulation results are verified and confirmed by laboratory experimental results using a scaled-down laboratory prototype setup.

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http://hdl.handle.net/10453/134761