Controllable reactor based hybrid HVDC breaker

Heidary, A; Bigdeli, M; Rouzbehi, K

Controllable reactor based hybrid HVDC breaker

Heidary, A Bigdeli, M Rouzbehi, K

Permalink

Publisher:: INST ENGINEERING TECHNOLOGY-IET
Publication Type:: Journal Article
Citation:: High Voltage, 2020, 5, (5), pp. 543-548
Issue Date:: 2020-10-01

Open Access

Copyright Clearance Process

Recently Added
In Progress
Open Access

This item is open access.

Adobe PDF

Download Published versionAdobe PDF (1.27 MB)

View on publisher's site

View statistics

Full metadata record

Field	Value	Language
dc.contributor.author	Heidary, A
dc.contributor.author	Bigdeli, M
dc.contributor.author	Rouzbehi, K https://orcid.org/0000-0002-3623-4840
dc.date.accessioned	2020-12-18T05:28:51Z
dc.date.available	2020-12-18T05:28:51Z
dc.date.issued	2020-10-01
dc.identifier.citation	High Voltage, 2020, 5, (5), pp. 543-548
dc.identifier.issn	2397-7264
dc.identifier.issn	2397-7264
dc.identifier.uri	http://hdl.handle.net/10453/144846
dc.description.abstract	© 2020 BMJ Publishing Group. All rights reserved. Short circuit fault occurrence in high-voltage DC (HVDC) systems causes extremely high currents in a fast raising time that does not experience current zero-crossing. To protect HVDC systems/grids against fault current, fast HVDC breaker is an essential equipment. This study presents the design procedure of a novel HVDC breaker based on solid-state controllable reactor which is able to reduce the fault current's rate of rise and fault current amplitude to less than grid nominal current in the breaking process. The main achievement of the proposed HVDC breaker is that not only breaker does not encounter fault current, but also none of the series HVDC equipment is influenced by the fault. The designed breaker performance is studied by PSCAD/EMTPS, and then the simulation results are validated by the developed laboratory experimental setup.
dc.language	English
dc.publisher	INST ENGINEERING TECHNOLOGY-IET
dc.relation.ispartof	High Voltage
dc.relation.isbasedon	10.1049/hve.2019.0354
dc.rights	This paper is a postprint of a paper submitted to and accepted for publication in High Voltage and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at the IET Digital Library.	en_US
dc.rights	info:eu-repo/semantics/openAccess
dc.rights	This is an open access article published by the IET and CEPRI under the Creative Commons Attribution-NoDerivs License(http://creativecommons.org/licenses/by-nd/3.0/)
dc.title	Controllable reactor based hybrid HVDC breaker
dc.type	Journal Article
utslib.citation.volume	5
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology/School of Electrical and Data Engineering
pubs.organisational-group	/University of Technology Sydney
utslib.copyright.status	open_access	*
dc.date.updated	2020-12-18T05:28:35Z
pubs.issue	5
pubs.publication-status	Published
pubs.volume	5
utslib.citation.issue	5

Abstract:

© 2020 BMJ Publishing Group. All rights reserved. Short circuit fault occurrence in high-voltage DC (HVDC) systems causes extremely high currents in a fast raising time that does not experience current zero-crossing. To protect HVDC systems/grids against fault current, fast HVDC breaker is an essential equipment. This study presents the design procedure of a novel HVDC breaker based on solid-state controllable reactor which is able to reduce the fault current's rate of rise and fault current amplitude to less than grid nominal current in the breaking process. The main achievement of the proposed HVDC breaker is that not only breaker does not encounter fault current, but also none of the series HVDC equipment is influenced by the fault. The designed breaker performance is studied by PSCAD/EMTPS, and then the simulation results are validated by the developed laboratory experimental setup.

Please use this identifier to cite or link to this item:

http://hdl.handle.net/10453/144846