Comparative Study of Phase Lead Compensator based In-loop Filtering Method in Single-Phase PLL
- Publisher:
- IEEE
- Publication Type:
- Conference Proceeding
- Citation:
- Proceedings IECON 2020 The 46th Annual Conference of the IEEE Industrial Electronics Society, 2020, 2020-October, pp. 4947-4954
- Issue Date:
- 2020-10-18
Closed Access
| Filename | Description | Size | |||
|---|---|---|---|---|---|
| 09255138.pdf | 4.04 MB |
Copyright Clearance Process
- Recently Added
- In Progress
- Closed Access
This item is closed access and not available.
Accurate estimation of grid voltage parameters (phase, frequency and amplitude) from Phase Locked Loop (PLL) is a challenging task under distorted and abnormal grid conditions. To equip PLLs in such scenarios, additional filters can be appended inside the control loop. The improvement in steady-state accuracy then comes in exchange of reduced control bandwidth because of phase delay introduced by filters. To boost the dynamic response, a preferred solution is cascading phase lead compensator (PLC) (with filters), while maintaining the disturbance rejection capability. This paper assesses performance of two types of PLCs (standard and digital) which are designed to minimize the phase delay of in-loop filters employed in PLL. These two approaches are compared by evaluating their dynamic response, steady-state accuracy and implementation complexity. The paper also provides design guidelines for both types of PLC along with its effect on controller design. The discussions presented are validated via simulation and experimental results.
Please use this identifier to cite or link to this item: