A switched-capacitors-based 13-level inverter

Bhatnagar, P; Singh, AK; Gupta, KK; Siwakoti, YP

A switched-capacitors-based 13-level inverter

Bhatnagar, P Singh, AK Gupta, KK Siwakoti, YP

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Publisher:: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Publication Type:: Journal Article
Citation:: IEEE Transactions on Power Electronics, 2022, 37, (1), pp. 644-658
Issue Date:: 2022-01-01

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Field	Value	Language
dc.contributor.author	Bhatnagar, P
dc.contributor.author	Singh, AK
dc.contributor.author	Gupta, KK
dc.contributor.author	Siwakoti, YP
dc.date.accessioned	2022-03-08T03:19:15Z
dc.date.available	2022-03-08T03:19:15Z
dc.date.issued	2022-01-01
dc.identifier.citation	IEEE Transactions on Power Electronics, 2022, 37, (1), pp. 644-658
dc.identifier.issn	0885-8993
dc.identifier.issn	1941-0107
dc.identifier.uri	http://hdl.handle.net/10453/155049
dc.description.abstract	The merit of switched-capacitors-based multilevel inverters (SCMLIs) is generally quantified in terms of a 'cost function' (CF) that incorporates parameters such as voltage gain, component count, total standing voltage (TSV), and number of levels. In this article, a 13-level inverter is proposed with the aim of achieving a low value of CF. The proposed single-stage SCMLI uses one input source and three capacitors to attain a voltage gain of 3. It requires 13 power switches, of which the peak inverse voltage (PIV) of nine switches is restricted to the source voltage. The remaining four switches have PIV equal to twice the source voltage and they operate at low frequency. Thus, for all switches, the PIV is less than the amplitude of the output voltage. Moreover, the capacitors are self-balanced at all regions of modulation index values. The proposed inverter is validated through simulation and experimental results. A comparison of the proposed topology with other contemporary SCMLIs shows that it is highly competent in terms of CF, PIV and TSV requirements, waveform resolution, and capability to achieve voltage balancing of capacitors at low values of modulation index.
dc.language	English
dc.publisher	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.relation.ispartof	IEEE Transactions on Power Electronics
dc.relation.isbasedon	10.1109/TPEL.2021.3098827
dc.rights	info:eu-repo/semantics/closedAccess
dc.subject	0906 Electrical and Electronic Engineering
dc.subject.classification	Electrical & Electronic Engineering
dc.title	A switched-capacitors-based 13-level inverter
dc.type	Journal Article
utslib.citation.volume	37
utslib.for	0906 Electrical and Electronic Engineering
pubs.organisational-group	/University of Technology Sydney
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology/School of Electrical and Data Engineering
utslib.copyright.status	closed_access	*
dc.date.updated	2022-03-08T03:19:11Z
pubs.issue	1
pubs.publication-status	Published
pubs.volume	37
utslib.citation.issue	1

Abstract:

The merit of switched-capacitors-based multilevel inverters (SCMLIs) is generally quantified in terms of a 'cost function' (CF) that incorporates parameters such as voltage gain, component count, total standing voltage (TSV), and number of levels. In this article, a 13-level inverter is proposed with the aim of achieving a low value of CF. The proposed single-stage SCMLI uses one input source and three capacitors to attain a voltage gain of 3. It requires 13 power switches, of which the peak inverse voltage (PIV) of nine switches is restricted to the source voltage. The remaining four switches have PIV equal to twice the source voltage and they operate at low frequency. Thus, for all switches, the PIV is less than the amplitude of the output voltage. Moreover, the capacitors are self-balanced at all regions of modulation index values. The proposed inverter is validated through simulation and experimental results. A comparison of the proposed topology with other contemporary SCMLIs shows that it is highly competent in terms of CF, PIV and TSV requirements, waveform resolution, and capability to achieve voltage balancing of capacitors at low values of modulation index.

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http://hdl.handle.net/10453/155049