Memristor-based Edge Computing of ShuffleNetV2 for Image Classification

Ran, H; Wen, S; Wang, S; Cao, Y; Zhou, P; Huang, T

Memristor-based Edge Computing of ShuffleNetV2 for Image Classification

Ran, H Wen, S

Wang, S Cao, Y Zhou, P Huang, T

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Publisher:: Institute of Electrical and Electronics Engineers
Publication Type:: Journal Article
Citation:: IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems, 2021, 40, (8), pp. 1701-1710
Issue Date:: 2021

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Field	Value	Language
dc.contributor.author	Ran, H
dc.contributor.author	Wen, S https://orcid.org/0000-0001-8077-7001
dc.contributor.author	Wang, S
dc.contributor.author	Cao, Y
dc.contributor.author	Zhou, P
dc.contributor.author	Huang, T
dc.date.accessioned	2022-04-27T03:50:42Z
dc.date.available	2022-04-27T03:50:42Z
dc.date.issued	2021
dc.identifier.citation	IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems, 2021, 40, (8), pp. 1701-1710
dc.identifier.issn	0278-0070
dc.identifier.issn	1937-4151
dc.identifier.uri	http://hdl.handle.net/10453/156646
dc.description.abstract	IEEE In this paper, we propose a memristor-based ShuffleNetV2 for image classification. Because of the low power consumption and high integration, this circuit is suitable for edge computing. The memristor-based ShuffleNetV2 is divided into four kinds of units, and each unit is composed by a series of basic memristive neural circuits, such as memristive Convolutional Neural Networks (MCNNs), Memristive Batch Normalization (MBN) layers, Memristive Fully Connection (MFC) layers, Rectified Linear Unit (ReLU) layers and max-pooling layers etc.. To solve the imbalance of required memristor crossbars in MCNN and the huge power consumption of the input voltage inverting, the inverters are shifted behind the memristor crossbar.This circuit uses (M+1)×2 memristor crossbars instead of the original (2M+1)×1 memristor crossbars. The world lines of memristor crossbars required can be reduced from (2M+1) to (M+1). The number of inverters in MCNN for a kernel can be decreased to one, and the power consumption in MCNN is greatly decreased. The MBN is designed by combining operational amplifiers with memristors. An output limiter circuit is added behind the ReLU layer implemented by diode. The output voltage of ReLU layer is limited to the threshold voltage Vp of memristor. The memristive ShuffleNetV2 is established for image classification in experiments. The effectiveness of the circuit is verified on the FER2013 dataset along with the analysis of the memristor resources, calculation periods and circuit power consumption of the network. The experimental results show that this that the inference time of this memristive ShuffleNetV2 could be as less as 137ns with a max power consumption 2.8μW of a memristive neurons.
dc.language	en
dc.publisher	Institute of Electrical and Electronics Engineers
dc.relation	National Natural Science Foundation of China61673187
dc.relation.ispartof	IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems
dc.relation.isbasedon	10.1109/TCAD.2020.3022970
dc.rights	info:eu-repo/semantics/closedAccess
dc.subject	0906 Electrical and Electronic Engineering, 1006 Computer Hardware
dc.subject.classification	Computer Hardware & Architecture
dc.title	Memristor-based Edge Computing of ShuffleNetV2 for Image Classification
dc.type	Journal Article
utslib.citation.volume	40
utslib.for	0906 Electrical and Electronic Engineering
utslib.for	1006 Computer Hardware
pubs.organisational-group	/University of Technology Sydney
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology
pubs.organisational-group	/University of Technology Sydney/Strength - AAII - Australian Artificial Intelligence Institute
utslib.copyright.status	closed_access	*
pubs.consider-herdc	false
dc.date.updated	2022-04-27T03:50:39Z
pubs.issue	8
pubs.publication-status	Published
pubs.volume	40
utslib.citation.issue	8

Abstract:

IEEE In this paper, we propose a memristor-based ShuffleNetV2 for image classification. Because of the low power consumption and high integration, this circuit is suitable for edge computing. The memristor-based ShuffleNetV2 is divided into four kinds of units, and each unit is composed by a series of basic memristive neural circuits, such as memristive Convolutional Neural Networks (MCNNs), Memristive Batch Normalization (MBN) layers, Memristive Fully Connection (MFC) layers, Rectified Linear Unit (ReLU) layers and max-pooling layers etc.. To solve the imbalance of required memristor crossbars in MCNN and the huge power consumption of the input voltage inverting, the inverters are shifted behind the memristor crossbar.This circuit uses (M+1)×2 memristor crossbars instead of the original (2M+1)×1 memristor crossbars. The world lines of memristor crossbars required can be reduced from (2M+1) to (M+1). The number of inverters in MCNN for a kernel can be decreased to one, and the power consumption in MCNN is greatly decreased. The MBN is designed by combining operational amplifiers with memristors. An output limiter circuit is added behind the ReLU layer implemented by diode. The output voltage of ReLU layer is limited to the threshold voltage Vp of memristor. The memristive ShuffleNetV2 is established for image classification in experiments. The effectiveness of the circuit is verified on the FER2013 dataset along with the analysis of the memristor resources, calculation periods and circuit power consumption of the network. The experimental results show that this that the inference time of this memristive ShuffleNetV2 could be as less as 137ns with a max power consumption 2.8μW of a memristive neurons.

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http://hdl.handle.net/10453/156646