A Two-Stage Analog Self-Interference Cancellation Structure for High Transmit Power In-Band Full-Duplex Radios

Le, AT; Huang, X; Guo, YJ

A Two-Stage Analog Self-Interference Cancellation Structure for High Transmit Power In-Band Full-Duplex Radios

Le, AT Huang, X

Guo, YJ

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Publisher:: Institute of Electrical and Electronics Engineers (IEEE)
Publication Type:: Journal Article
Citation:: IEEE Wireless Communications Letters, 2022, PP, (99), pp. 1-1
Issue Date:: 2022-09-12

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Full metadata record

Field	Value	Language
dc.contributor.author	Le, AT
dc.contributor.author	Huang, X https://orcid.org/0000-0001-6869-5732
dc.contributor.author	Guo, YJ
dc.date.accessioned	2022-09-20T06:53:57Z
dc.date.available	2022-09-20T06:53:57Z
dc.date.issued	2022-09-12
dc.identifier.citation	IEEE Wireless Communications Letters, 2022, PP, (99), pp. 1-1
dc.identifier.issn	2162-2337
dc.identifier.issn	2162-2345
dc.identifier.uri	http://hdl.handle.net/10453/161924
dc.language	en
dc.publisher	Institute of Electrical and Electronics Engineers (IEEE)
dc.relation	http://purl.org/au-research/grants/arc/DP200101532
dc.relation	University of Technology Sydney
dc.relation.ispartof	IEEE Wireless Communications Letters
dc.relation.isbasedon	10.1109/lwc.2022.3205600
dc.rights	info:eu-repo/semantics/embargoedAccess
dc.subject	0805 Distributed Computing, 0906 Electrical and Electronic Engineering, 1005 Communications Technologies
dc.title	A Two-Stage Analog Self-Interference Cancellation Structure for High Transmit Power In-Band Full-Duplex Radios
dc.type	Journal Article
utslib.citation.volume	PP
utslib.for	0805 Distributed Computing
utslib.for	0906 Electrical and Electronic Engineering
utslib.for	1005 Communications Technologies
pubs.organisational-group	/University of Technology Sydney
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology
pubs.organisational-group	/University of Technology Sydney/Strength - GBDTC - Global Big Data Technologies
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology/School of Electrical and Data Engineering
utslib.copyright.status	open_access	*
utslib.copyright.embargo	2024-09-12T00:00:00+1000Z
dc.date.updated	2022-09-20T06:53:56Z
pubs.issue	99
pubs.publication-status	Published
pubs.volume	PP
utslib.citation.issue	99

Please use this identifier to cite or link to this item:

http://hdl.handle.net/10453/161924