Symmetrical Multilayer Dielectric Model of Thermal Stress and Strain of Silicon-Core Coaxial Through-Silicon Vias in 3-D Integrated Circuit
- Publisher:
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Publication Type:
- Journal Article
- Citation:
- IEEE Transactions on Components, Packaging and Manufacturing Technology, 2022, 12, (7), pp. 1122-1129
- Issue Date:
- 2022-07-01
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In this work, an analytical model of strain and stress of symmetrical multilayer medium is proposed to solve the thermal problem that occurs in silicon-core coaxial through-silicon vias (S-CTSV). Based on the 3-D Kane-Mindlin theory, the proposed analytical model of strain considers both elastic strain and thermal strain. In addition, the stress is discussed in segments using planar stress and Hooke's law in the model of S-CTSVs to improve the accuracy. The results indicate that the average relative errors in terms of strain and stress between the results of the proposed analytical model and the finite-element method (FEM) were 4.06% and 0.17%, respectively. Compared with the back propagation (BP) neural network-based prediction algorithm, the average relative errors in strain and stress between the proposed model and the FEM were decreased by 3.97% and 3.23%, respectively. Moreover, the stress of three different CTSVs was also compared. The stress of the proposed S-CTSVs model was lower than those of the two traditional CTSVs, which ensure higher reliability. The results in this article would provide some design guides for S-CTSVs in 3-D integration.
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