A W-Band SPDT Switch With 15-dBm P1dB in 55-nm Bulk CMOS

Chen, L; Chen, L; Ge, Z; Sun, Y; Hamilton, T; Zhu, X

A W-Band SPDT Switch With 15-dBm P1dB in 55-nm Bulk CMOS

Chen, L Chen, L Ge, Z Sun, Y Hamilton, T

Zhu, X

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Publisher:: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Publication Type:: Journal Article
Citation:: IEEE Microwave and Wireless Components Letters, 2022, 32, (7), pp. 879-882
Issue Date:: 2022-07-01

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Field	Value	Language
dc.contributor.author	Chen, L
dc.contributor.author	Chen, L
dc.contributor.author	Ge, Z
dc.contributor.author	Sun, Y
dc.contributor.author	Hamilton, T https://orcid.org/0000-0003-2630-7011
dc.contributor.author	Zhu, X https://orcid.org/0000-0002-5814-394X
dc.date.accessioned	2023-03-19T23:52:07Z
dc.date.available	2023-03-19T23:52:07Z
dc.date.issued	2022-07-01
dc.identifier.citation	IEEE Microwave and Wireless Components Letters, 2022, 32, (7), pp. 879-882
dc.identifier.issn	1531-1309
dc.identifier.issn	1558-1764
dc.identifier.uri	http://hdl.handle.net/10453/167633
dc.description.abstract	Power-handling capability of bulk CMOS-based single-pole double-throw (SPDT) switch operating in millimeter-wave (mm-wave) and subterahertz region is significantly limited by the reduced threshold voltage of deeply scaled transistors. A unique design technique based on impedance transformation network (ITN) is presented in this work, which improves 1-dB compression point, namely P1dB, without deteriorating other performance. To prove the presented solution is valid, a 70-100-GHz switch is designed and implemented in a 55-nm bulk CMOS technology. At 90 GHz, it achieves a measured P1dB of 15 dBm, an insertion loss (IL) of 3.5 dB, and an isolation (ISO) of 18 dB. The total area of the chip is only 0.14 mm2.
dc.language	English
dc.publisher	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.relation	Sydnicon RF Pty Ltd
dc.relation.ispartof	IEEE Microwave and Wireless Components Letters
dc.relation.isbasedon	10.1109/LMWC.2022.3159529
dc.rights	info:eu-repo/semantics/closedAccess
dc.subject	0205 Optical Physics, 0906 Electrical and Electronic Engineering, 1005 Communications Technologies
dc.subject.classification	Networking & Telecommunications
dc.title	A W-Band SPDT Switch With 15-dBm P1dB in 55-nm Bulk CMOS
dc.type	Journal Article
utslib.citation.volume	32
utslib.for	0205 Optical Physics
utslib.for	0906 Electrical and Electronic Engineering
utslib.for	1005 Communications Technologies
pubs.organisational-group	/University of Technology Sydney
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology
pubs.organisational-group	/University of Technology Sydney/Strength - GBDTC - Global Big Data Technologies
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology/School of Electrical and Data Engineering
utslib.copyright.status	closed_access	*
dc.date.updated	2023-03-19T23:52:06Z
pubs.issue	7
pubs.publication-status	Published
pubs.volume	32
utslib.citation.issue	7

Abstract:

Power-handling capability of bulk CMOS-based single-pole double-throw (SPDT) switch operating in millimeter-wave (mm-wave) and subterahertz region is significantly limited by the reduced threshold voltage of deeply scaled transistors. A unique design technique based on impedance transformation network (ITN) is presented in this work, which improves 1-dB compression point, namely P1dB, without deteriorating other performance. To prove the presented solution is valid, a 70-100-GHz switch is designed and implemented in a 55-nm bulk CMOS technology. At 90 GHz, it achieves a measured P1dB of 15 dBm, an insertion loss (IL) of 3.5 dB, and an isolation (ISO) of 18 dB. The total area of the chip is only 0.14 mm2.

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http://hdl.handle.net/10453/167633