Ultra Compact and Linear 4-bit Digital-to-Analog Converter in 22nm FDSOI Technology

Eslahi, H; Hamilton, TJ; Khandelwal, S

Ultra Compact and Linear 4-bit Digital-to-Analog Converter in 22nm FDSOI Technology

Eslahi, H Hamilton, TJ Khandelwal, S

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Publisher:: Institute of Electrical and Electronics Engineers (IEEE)
Publication Type:: Conference Proceeding
Citation:: Proceedings - IEEE International Symposium on Circuits and Systems, 2022, 2022-May, pp. 2778-2781
Issue Date:: 2022-01-01

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Field	Value	Language
dc.contributor.author	Eslahi, H
dc.contributor.author	Hamilton, TJ
dc.contributor.author	Khandelwal, S
dc.date	2022-05-27
dc.date.accessioned	2023-04-13T03:36:59Z
dc.date.available	2023-04-13T03:36:59Z
dc.date.issued	2022-01-01
dc.identifier.citation	Proceedings - IEEE International Symposium on Circuits and Systems, 2022, 2022-May, pp. 2778-2781
dc.identifier.isbn	9781665484855
dc.identifier.issn	0271-4310
dc.identifier.uri	http://hdl.handle.net/10453/169744
dc.description.abstract	This work presents two 4-bit resistor-string digital-to-analog converters (R-DAC) designed in 22nm FDSOI technology. Both DACs are connected to a shared resistor string to make the final layout more compact. The small on-resistance of the Transmission-Gate (TG) switches designed in the FDSOI node yields a low Internal non-linearity (INL) and Differential non-linearity (DNL) in the DACs output. The effect of the temperature variations on the linearity performance of the DACs is also studied. It is shown that the temperature gradients can be compensated for by equally distributing the switches on the layout area. Post-layout simulations show an approximately fixed INL and DNL of, respectively, 0. 17LSB and 0. 1LSB over a wide temperature range from-40°C to 125{0} C. Two R-DACs dissipate the static/dynamic power of 0. 12/0.155mW with the layout size of only 70 mu m{2}, showing a high performance for two 4-bit DACs.
dc.language	en
dc.publisher	Institute of Electrical and Electronics Engineers (IEEE)
dc.relation.ispartof	Proceedings - IEEE International Symposium on Circuits and Systems
dc.relation.ispartof	2022 IEEE International Symposium on Circuits and Systems (ISCAS)
dc.relation.isbasedon	10.1109/ISCAS48785.2022.9937686
dc.rights	info:eu-repo/semantics/closedAccess
dc.title	Ultra Compact and Linear 4-bit Digital-to-Analog Converter in 22nm FDSOI Technology
dc.type	Conference Proceeding
utslib.citation.volume	2022-May
pubs.organisational-group	/University of Technology Sydney
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology/School of Electrical and Data Engineering
utslib.copyright.status	closed_access	*
dc.date.updated	2023-04-13T03:36:57Z
pubs.finish-date	2022-06-01
pubs.publication-status	Published
pubs.start-date	2022-05-27
pubs.volume	2022-May

Abstract:

This work presents two 4-bit resistor-string digital-to-analog converters (R-DAC) designed in 22nm FDSOI technology. Both DACs are connected to a shared resistor string to make the final layout more compact. The small on-resistance of the Transmission-Gate (TG) switches designed in the FDSOI node yields a low Internal non-linearity (INL) and Differential non-linearity (DNL) in the DACs output. The effect of the temperature variations on the linearity performance of the DACs is also studied. It is shown that the temperature gradients can be compensated for by equally distributing the switches on the layout area. Post-layout simulations show an approximately fixed INL and DNL of, respectively, 0. 17LSB and 0. 1LSB over a wide temperature range from-40°C to 125{0} C. Two R-DACs dissipate the static/dynamic power of 0. 12/0.155mW with the layout size of only 70 mu m{2}, showing a high performance for two 4-bit DACs.

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http://hdl.handle.net/10453/169744