A 40-GHz Load Modulated Balanced Power Amplifier Using Unequal Power Splitter and Phase Compensation Network in 45-nm SOI CMOS

Chen, L; Chen, L; Ge, Z; Sun, Y; Zhu, X

A 40-GHz Load Modulated Balanced Power Amplifier Using Unequal Power Splitter and Phase Compensation Network in 45-nm SOI CMOS

Chen, L Chen, L Ge, Z Sun, Y Zhu, X

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Publisher:: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Publication Type:: Journal Article
Citation:: IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70, (8), pp. 3178-3186
Issue Date:: 2023-08-01

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Field	Value	Language
dc.contributor.author	Chen, L
dc.contributor.author	Chen, L
dc.contributor.author	Ge, Z
dc.contributor.author	Sun, Y
dc.contributor.author	Zhu, X https://orcid.org/0000-0002-5814-394X
dc.date.accessioned	2024-03-04T23:31:10Z
dc.date.available	2024-03-04T23:31:10Z
dc.date.issued	2023-08-01
dc.identifier.citation	IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70, (8), pp. 3178-3186
dc.identifier.issn	1549-8328
dc.identifier.issn	1558-0806
dc.identifier.uri	http://hdl.handle.net/10453/176094
dc.description.abstract	In this work, a ten-way power-combined power amplifier is designed using a load modulated balanced amplifier (LMBA)-based architecture. To provide the required magnitude and phase controls between the main and control-signal paths of the LMBA, an unequal power splitter and a phase compensation network are proposed. As proof of concept, the designed power amplifier is implemented in a 45-nm SOI CMOS process. At 40 GHz, it delivers a 25.1 dBm Psat with a peak power-added efficiency (PAE) of 27.9%. At 6-dB power back-off level, it achieves 1.39 times drain efficiency enhancement over an ideal Class-B power amplifier. Using a 200-MHz single-carrier 64-QAM signal, the designed amplifier delivers an average output power of 16.5 dBm with a PAE of 13.1% at an EVMrms of -23.9 dB and ACPR of -25.3 dBc. The die size, including all testing pads, is only 1.92 mm2. To the best of the authors' knowledge, compared with the other recently published silicon-based LMBAs, this design achieves the highest Psat.
dc.language	English
dc.publisher	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.relation	http://purl.org/au-research/grants/arc/LP210100378
dc.relation	Department of Industry, Innovation and ScienceICG001429
dc.relation.ispartof	IEEE Transactions on Circuits and Systems I: Regular Papers
dc.relation.isbasedon	10.1109/TCSI.2023.3282731
dc.rights	info:eu-repo/semantics/closedAccess
dc.subject	0906 Electrical and Electronic Engineering
dc.subject.classification	Electrical & Electronic Engineering
dc.subject.classification	4009 Electronics, sensors and digital hardware
dc.title	A 40-GHz Load Modulated Balanced Power Amplifier Using Unequal Power Splitter and Phase Compensation Network in 45-nm SOI CMOS
dc.type	Journal Article
utslib.citation.volume	70
utslib.for	0906 Electrical and Electronic Engineering
pubs.organisational-group	University of Technology Sydney
pubs.organisational-group	University of Technology Sydney/Faculty of Engineering and Information Technology
pubs.organisational-group	University of Technology Sydney/Strength - GBDTC - Global Big Data Technologies
pubs.organisational-group	University of Technology Sydney/Faculty of Engineering and Information Technology/School of Electrical and Data Engineering
utslib.copyright.status	closed_access	*
dc.date.updated	2024-03-04T23:31:06Z
pubs.issue	8
pubs.publication-status	Published
pubs.volume	70
utslib.citation.issue	8

Abstract:

In this work, a ten-way power-combined power amplifier is designed using a load modulated balanced amplifier (LMBA)-based architecture. To provide the required magnitude and phase controls between the main and control-signal paths of the LMBA, an unequal power splitter and a phase compensation network are proposed. As proof of concept, the designed power amplifier is implemented in a 45-nm SOI CMOS process. At 40 GHz, it delivers a 25.1 dBm Psat with a peak power-added efficiency (PAE) of 27.9%. At 6-dB power back-off level, it achieves 1.39 times drain efficiency enhancement over an ideal Class-B power amplifier. Using a 200-MHz single-carrier 64-QAM signal, the designed amplifier delivers an average output power of 16.5 dBm with a PAE of 13.1% at an EVMrms of -23.9 dB and ACPR of -25.3 dBc. The die size, including all testing pads, is only 1.92 mm2. To the best of the authors' knowledge, compared with the other recently published silicon-based LMBAs, this design achieves the highest Psat.

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http://hdl.handle.net/10453/176094