HyBNN: Quantifying and Optimizing Hardware Efficiency of Binary Neural Networks

Yang, G; Lei, J; Fang, Z; Li, Y; Zhang, J; Xie, W

HyBNN: Quantifying and Optimizing Hardware Efficiency of Binary Neural Networks

Yang, G Lei, J

Fang, Z Li, Y Zhang, J Xie, W

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Publisher:: IEEE
Publication Type:: Conference Proceeding
Citation:: 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2023, 00, pp. 203
Issue Date:: 2023-07-10

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Field	Value	Language
dc.contributor.author	Yang, G
dc.contributor.author	Lei, J https://orcid.org/0000-0003-0851-6565
dc.contributor.author	Fang, Z
dc.contributor.author	Li, Y
dc.contributor.author	Zhang, J
dc.contributor.author	Xie, W
dc.date	2023-05-08
dc.date.accessioned	2024-05-13T04:36:47Z
dc.date.available	2024-05-13T04:36:47Z
dc.date.issued	2023-07-10
dc.identifier.citation	2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2023, 00, pp. 203
dc.identifier.isbn	979-8-3503-1206-5
dc.identifier.issn	2576-2613
dc.identifier.uri	http://hdl.handle.net/10453/178932
dc.description.abstract	Binary neural network BNN has recently presented a promising opportunity for deep learning inferences on resource constrained edge devices Using extreme data precision i e 1 bit weight and 1 bit activation BNN not only significantly reduces the network memory footprint but also trades massive multiply accumulate operations for much cheaper logical XNOR and population count operations However our investigation reveals that to achieve satisfactory accuracy gains state of the art SOTA BNNs such as FracBNN 4 and ReActNet 1 usually have to incorporate various auxiliary floating point AFP components and increase the model size which in turn degrades the hardware performance efficiency
dc.language	en
dc.publisher	IEEE
dc.relation.ispartof	2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
dc.relation.ispartof	2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines
dc.relation.isbasedon	10.1109/fccm57271.2023.00031
dc.rights	info:eu-repo/semantics/closedAccess
dc.title	HyBNN: Quantifying and Optimizing Hardware Efficiency of Binary Neural Networks
dc.type	Conference Proceeding
utslib.citation.volume	00
utslib.location.activity	Marina Del Rey, CA, USA
pubs.organisational-group	University of Technology Sydney
pubs.organisational-group	University of Technology Sydney/Faculty of Engineering and Information Technology
pubs.organisational-group	University of Technology Sydney/Faculty of Engineering and Information Technology/School of Electrical and Data Engineering
utslib.copyright.status	closed_access	*
dc.date.updated	2024-05-13T04:36:46Z
pubs.finish-date	2023-05-11
pubs.place-of-publication	Piscataway, USA
pubs.publication-status	Published
pubs.start-date	2023-05-08
pubs.volume	00
dc.location	Piscataway, USA

Abstract:

Binary neural network BNN has recently presented a promising opportunity for deep learning inferences on resource constrained edge devices Using extreme data precision i e 1 bit weight and 1 bit activation BNN not only significantly reduces the network memory footprint but also trades massive multiply accumulate operations for much cheaper logical XNOR and population count operations However our investigation reveals that to achieve satisfactory accuracy gains state of the art SOTA BNNs such as FracBNN 4 and ReActNet 1 usually have to incorporate various auxiliary floating point AFP components and increase the model size which in turn degrades the hardware performance efficiency

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http://hdl.handle.net/10453/178932