Acquisition Performance of a Digital Phase Locked Loop with a Four-Quadrant Arctan Phase Detector

Sithamparanathan, K; Reisenfeld, S

Acquisition Performance of a Digital Phase Locked Loop with a Four-Quadrant Arctan Phase Detector

Sithamparanathan, K Reisenfeld, S

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Publisher:: ISPACS Committee
Publication Type:: Conference Proceeding
Citation:: ISPACS 2004 Proceedings, 2004, pp. 1 - 5
Issue Date:: 2004-01

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Field	Value	Language
dc.contributor.author	Sithamparanathan, K	en_US
dc.contributor.author	Reisenfeld, S	en_US
dc.contributor.editor	NA	en_US
dc.date	2004-11-18	en_US
dc.date.issued	2004-01	en_US
dc.identifier.citation	ISPACS 2004 Proceedings, 2004, pp. 1 - 5	en_US
dc.identifier.isbn	0-7803-8640-X	en_US
dc.identifier.uri	http://hdl.handle.net/10453/3028
dc.description.abstract	The acquisition performance of a digital phase locked loop (DPLL) with a four-quadrant arctan based phase detector (PD) is discussed. In the noiseless case, unlike the traditional sine function based phase locked loops, the acquisition process of the four-quadrant arctan based phase locked loops is less tedious. We look into the pull-in process together with a time-series analysis of the DPLL for the noiseless case. The phase-plane portrait of the loop is also discussed, for both the noiseless and the noisy conditions.	en_US
dc.publisher	ISPACS Committee	en_US
dc.relation.ispartof	ISPACS 2004 Proceedings	en_US
dc.relation.ispartof	International Symposium on Intelligent Signal Processing and Communications Systems	en_US
dc.relation.isbasedon	10.1109/ISPACS.2004.1439139	en_US
dc.title	Acquisition Performance of a Digital Phase Locked Loop with a Four-Quadrant Arctan Phase Detector	en_US
dc.type	Conference Proceeding
utslib.location	Seoul, Korea	en_US
utslib.location.activity	Seoul, Korea	en_US
utslib.for	0906 Electrical and Electronic Engineering	en_US
dc.location.activity	Seoul, Korea	en_US
pubs.embargo.period	Not known	en_US
pubs.organisational-group	/University of Technology Sydney
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology/School of Electrical and Data Engineering
utslib.copyright.status	closed_access
pubs.consider-herdc	true	en_US
pubs.place-of-publication	Seoul, Korea	en_US
pubs.start-date	2004-11-18	en_US

Abstract:

The acquisition performance of a digital phase locked loop (DPLL) with a four-quadrant arctan based phase detector (PD) is discussed. In the noiseless case, unlike the traditional sine function based phase locked loops, the acquisition process of the four-quadrant arctan based phase locked loops is less tedious. We look into the pull-in process together with a time-series analysis of the DPLL for the noiseless case. The phase-plane portrait of the loop is also discussed, for both the noiseless and the noisy conditions.

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http://hdl.handle.net/10453/3028