MODELING AND EVALUATION OF CACHE COHERENCE MECHANISMS FOR MULTICORE PROCESSORS

Al-Manasia, MA

MODELING AND EVALUATION OF CACHE COHERENCE MECHANISMS FOR MULTICORE PROCESSORS

Al-Manasia, MA

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Citation:: 2011
Issue Date:: 2011-04-17

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Field	Value	Language
dc.contributor.author	Al-Manasia, MA	en_US
dc.contributor.editor	Dr. FARUQ AL-OMARI, FA	en_US
dc.date.issued	2011-04-17	en_US
dc.date.submitted	2011-02-17	en_US
dc.identifier.citation	2011	en_US
dc.identifier.uri	http://hdl.handle.net/10453/62777
dc.description.abstract	Multicore computing have presented many challenges for system designers; one of which is data consistency between a shared cache or memory and the local caches of the chip. This is also known as cache coherency. The cache coherence mechanisms are a key component in the direction of accomplishing the goal of continuing exponential performance growth through widespread thread-level parallelism. In the scope of this research, we have studied the available efficient methods and protocols used to achieve cache coherence in multicore architectures. These protocols were further modelled and evaluated utilizing simics simulator for multicore architectures. We also investigated the weaknesses and strengths of different protocols and discussed the way of improving them.	en_US
dc.relation.ispartof	17/02/2011	en_US
dc.title	MODELING AND EVALUATION OF CACHE COHERENCE MECHANISMS FOR MULTICORE PROCESSORS	en_US
pubs.embargo.period	Not known	en_US
pubs.organisational-group	/University of Technology Sydney
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology
pubs.organisational-group	/University of Technology Sydney/Students
utslib.copyright.status	closed_access
pubs.filed-date	2011-02-17	en_US

Abstract:

Multicore computing have presented many challenges for system designers; one of which is data consistency between a shared cache or memory and the local caches of the chip. This is also known as cache coherency. The cache coherence mechanisms are a key component in the direction of accomplishing the goal of continuing exponential performance growth through widespread thread-level parallelism. In the scope of this research, we have studied the available efficient methods and protocols used to achieve cache coherence in multicore architectures. These protocols were further modelled and evaluated utilizing simics simulator for multicore architectures. We also investigated the weaknesses and strengths of different protocols and discussed the way of improving them.

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http://hdl.handle.net/10453/62777