Design of MIMO Testbed with an FPGA Board for Fast Signal Processing

Postula, A; Bialkowski, ME; Bialkowski, KS; Uthansakul, P

Design of MIMO Testbed with an FPGA Board for Fast Signal Processing

Postula, A Bialkowski, ME Bialkowski, KS Uthansakul, P

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Publication Type:: Conference
Issue Date:: 2007-03-12T22:05:33Z

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Field	Value	Language
dc.contributor.author	Postula, A	en_AU
dc.contributor.author	Bialkowski, ME	en_AU
dc.contributor.author	Bialkowski, KS	en_AU
dc.contributor.author	Uthansakul, P	en_AU
dc.date.accessioned	2007-03-12T22:05:33Z
dc.date.accessioned	2012-12-15T02:29:41Z
dc.date.available	2007-03-12T22:05:33Z
dc.date.available	2012-12-15T02:29:41Z
dc.date.issued	2007-03-12T22:05:33Z
dc.identifier.uri	http://hdl.handle.net/10453/19648
dc.description.abstract	This paper describes the design of a Multiple Input Multiple Output testbed for assessing various MIMO transmission schemes in rich scattering indoor environments. In the undertaken design, a Field Programmable Gate Array (FPGA) board is used for fast processing of Intermediate Frequency signals. At the present stage, the testbed performance is assessed when the channel emulator between transmitter and receiver modules is introduced. Here, the results are presented for the case when a 2x2 Alamouti scheme for space time coding/decoding at transmitter and receiver is used. Various programming details of the FPGA board along with the obtained simulation results are reported	en_AU
dc.format.extent	424395 bytes
dc.format.mimetype	application/pdf
dc.language.iso	en_AU
dc.relation.replaces	http://hdl.handle.net/2100/86
dc.title	Design of MIMO Testbed with an FPGA Board for Fast Signal Processing	en_AU
dc.type	Conference
utslib.copyright.status	open_access

Abstract:

This paper describes the design of a Multiple Input Multiple Output testbed for assessing various MIMO transmission schemes in rich scattering indoor environments. In the undertaken design, a Field Programmable Gate Array (FPGA) board is used for fast processing of Intermediate Frequency signals. At the present stage, the testbed performance is assessed when the channel emulator between transmitter and receiver modules is introduced. Here, the results are presented for the case when a 2x2 Alamouti scheme for space time coding/decoding at transmitter and receiver is used. Various programming details of the FPGA board along with the obtained simulation results are reported

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http://hdl.handle.net/10453/19648