An Asymmetrical Step-Up Multilevel Inverter Based on Switched-Capacitor Network

Taghvaie, A

Alijani, A Adabi, ME Rezanejad, M

Adabi, J Rouzbehi, K

Pouresmaeil, E

Permalink

Open Access

Copyright Clearance Process

This item is open access.

View statistics

Full metadata record

Field	Value	Language
dc.contributor.author	Taghvaie, A https://orcid.org/0000-0003-0455-9664	en_US
dc.contributor.author	Alijani, A	en_US
dc.contributor.author	Adabi, ME	en_US
dc.contributor.author	Rezanejad, M https://orcid.org/0000-0002-5432-759X	en_US
dc.contributor.author	Adabi, J	en_US
dc.contributor.author	Rouzbehi, K https://orcid.org/0000-0002-3623-4840	en_US
dc.contributor.author	Pouresmaeil, E https://orcid.org/0000-0003-2217-5293	en_US
dc.date.issued	2019-06-02	en_US
dc.identifier.citation	SUSTAINABILITY, 2019, 11 (12), pp. ? - ? (18)	en_US
dc.identifier.issn	2071-1050	en_US
dc.identifier.uri	http://hdl.handle.net/10453/134859
dc.language	English	en_US
dc.publisher	MDPI	en_US
dc.relation.ispartof	SUSTAINABILITY	en_US
dc.relation.isbasedon	10.3390/su11123453	en_US
dc.rights	info:eu-repo/semantics/openAccess
dc.title	An Asymmetrical Step-Up Multilevel Inverter Based on Switched-Capacitor Network	en_US
dc.type	Journal Article
utslib.citation.volume	12	en_US
utslib.citation.volume	11	en_US
utslib.for	12 Built Environment and Design	en_US
pubs.embargo.period	Not known	en_US
pubs.organisational-group	/University of Technology Sydney
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology/School of Electrical and Data Engineering
utslib.copyright.status	open_access	*
pubs.issue	12	en_US
pubs.publication-status	Published	en_US
pubs.volume	11	en_US

Please use this identifier to cite or link to this item: