Topology, Modeling and Control Scheme for a new Seven-Level Inverter with Reduced DC-Link Voltage

Khan, SA; Barzegarkhoo, R; Guo, Y; Siwakoti, Y; Khan, MNH; Lu, DDC; Zhu, J

Topology, Modeling and Control Scheme for a new Seven-Level Inverter with Reduced DC-Link Voltage

Khan, SA Barzegarkhoo, R Guo, Y

Siwakoti, Y

Khan, MNH Lu, DDC Zhu, J

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Publisher:: Institute of Electrical and Electronics Engineers
Publication Type:: Journal Article
Citation:: IEEE Transactions on Energy Conversion, 2021, 36, (4), pp. 2734-2746
Issue Date:: 2021-12-01

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Field	Value	Language
dc.contributor.author	Khan, SA
dc.contributor.author	Barzegarkhoo, R
dc.contributor.author	Guo, Y https://orcid.org/0000-0001-6182-0684
dc.contributor.author	Siwakoti, Y https://orcid.org/0000-0002-3869-412X
dc.contributor.author	Khan, MNH
dc.contributor.author	Lu, DDC
dc.contributor.author	Zhu, J https://orcid.org/0000-0002-9763-4047
dc.date.accessioned	2022-03-21T05:24:22Z
dc.date.available	2022-03-21T05:24:22Z
dc.date.issued	2021-12-01
dc.identifier.citation	IEEE Transactions on Energy Conversion, 2021, 36, (4), pp. 2734-2746
dc.identifier.issn	0885-8969
dc.identifier.issn	1558-0059
dc.identifier.uri	http://hdl.handle.net/10453/155434
dc.description.abstract	This paper presents a new single-source three-phase seven-level inverter with an inherent three-time voltage boosting capability for medium-voltage applications. The proposed topology is comprised of series connection of two switched-capacitor (SC) networks with an added half-bridge module per phase. Each of such integrated SC networks requires a single capacitor associated with three active power switches. The three-time voltage boosting feature of the proposed topology can reduce the dc-link voltage requirements by 50% in comparison to the traditional neutral point clamped (NPC), flying capacitors, active NPC (ANPC), hybrid clamped ANPC, and cascaded H-bridge topologies, and 75% to advanced ANPC topologies. It can also reduce the number of required switches and capacitors as well as their voltage stresses compared to those state-of-the-art topologies reported in the literature. By integrating 'n' number of added SC networks in the proposed seven-level basic topology, the number of output voltage levels can be extended to 2n+3 per phase. A finite control set model predictive control algorithm is also derived to control the converter in both the active and reactive power exchanges modes without distorting the generated grid current quality. The capacitor voltage balancing is inherent in the proposed topology, and thus, there is no need for any additional voltage balancing circuit, which further reduces the control complexity. The performance of the proposed topology and its control algorithm are validated by several measurement results.
dc.language	English
dc.publisher	Institute of Electrical and Electronics Engineers
dc.relation.ispartof	IEEE Transactions on Energy Conversion
dc.relation.isbasedon	10.1109/TEC.2021.3075964
dc.rights	info:eu-repo/semantics/embargoedAccess
dc.subject	0906 Electrical and Electronic Engineering
dc.subject.classification	Electrical & Electronic Engineering
dc.title	Topology, Modeling and Control Scheme for a new Seven-Level Inverter with Reduced DC-Link Voltage
dc.type	Journal Article
utslib.citation.volume	36
utslib.for	0906 Electrical and Electronic Engineering
pubs.organisational-group	/University of Technology Sydney
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology
pubs.organisational-group	/University of Technology Sydney/Strength - CCET - Centre for Clean Energy Technology
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology/School of Electrical and Data Engineering
utslib.copyright.status	open_access	*
pubs.consider-herdc	false
utslib.copyright.embargo	2023-04-27T00:00:00+1000Z
dc.date.updated	2022-03-21T05:24:17Z
pubs.issue	4
pubs.publication-status	Published
pubs.volume	36
utslib.citation.issue	4

Abstract:

This paper presents a new single-source three-phase seven-level inverter with an inherent three-time voltage boosting capability for medium-voltage applications. The proposed topology is comprised of series connection of two switched-capacitor (SC) networks with an added half-bridge module per phase. Each of such integrated SC networks requires a single capacitor associated with three active power switches. The three-time voltage boosting feature of the proposed topology can reduce the dc-link voltage requirements by 50% in comparison to the traditional neutral point clamped (NPC), flying capacitors, active NPC (ANPC), hybrid clamped ANPC, and cascaded H-bridge topologies, and 75% to advanced ANPC topologies. It can also reduce the number of required switches and capacitors as well as their voltage stresses compared to those state-of-the-art topologies reported in the literature. By integrating 'n' number of added SC networks in the proposed seven-level basic topology, the number of output voltage levels can be extended to 2n+3 per phase. A finite control set model predictive control algorithm is also derived to control the converter in both the active and reactive power exchanges modes without distorting the generated grid current quality. The capacitor voltage balancing is inherent in the proposed topology, and thus, there is no need for any additional voltage balancing circuit, which further reduces the control complexity. The performance of the proposed topology and its control algorithm are validated by several measurement results.

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http://hdl.handle.net/10453/155434