Design of Fully Integrated Load Modulation Balanced Power Amplifier

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As the 5G era makes more inroads into technology that dominates our lives, the demand for energy-efficient linear radio frequency (RF) power amplifier (PA) has continued to rise without showing any signs of stopping. The efficiency of PA, not only peak efficiency, but also efficiency at power back-off (PBO), is increasingly required to be enhanced. This demand is driven by the high spectral efficiency of modern communication standards, which leads to signals with a high peak-to-average power ratio (PAPR). To overcome this problem, a load modulation balanced amplifier (LMBA) structure was proposed by Steve Cripps in 2016. This new structure offers a new way to design back-off efficiency enhancement PA. This thesis attempts to explore this new structure for on-chip implementation, namely gallium arsenate (GaAs) and silicon-on-isolation (SOI) processes. The first design is a PA using a simple but effective architecture. This architecture can achieve not only a relatively high saturated output power, but also an excellent efficiency enhancement at PBO region. To prove the presented approach is feasible in practice, a PA is designed in a 1-μm GaAs HBT process. Operating under a 5-V power supply, the PA can deliver more than 31 dBm saturated output power (Psat) with 36% collector efficiency (CE) at 5 GHz. Moreover, it achieves 1.2- and 1.23- times CE enhancement over an ideal Class-B PA at 6- and 9-dB PBO levels, respectively. In the second study, to demonstrate the large output power of LMBA structure in silicon integrated circuits and millimeter wave, an 8-way combined LMBA PA is designed. With 2-V power supply, the PA can deliver more than 25.1 dBm Psat at 40 GHz. The peak power added efficiency (PAE) and PAE at 6-dB PBO level are better than 27.9% and 19%, respectively. Additionally, at 6-dB PBO level, the designed LMBA achieves 1.39-times drain efficiency (DE) enhancement over an ideal Class-B PA operating at 40 GHz, respectively. In the third work, to overcome the influence of non-50 Ω isolation, a double coupler structure is proposed and fabricated in 45 nm CMOS SOI process. Through the use of 1.2 V supply voltage, it can achieve 22.1 dBm Psat, peak PAE of 25.7% and 6 dB PBO PAE of 21.8% at 39 GHz. Compared with an ideal Class-B PA, the DE improves 1.68 times at 6 dB PBO.
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