FPGA-based sensorless PMSM speed control using reduced-order extended kalman filters

Quang, NK; Hieu, NT; Ha, QP

FPGA-based sensorless PMSM speed control using reduced-order extended kalman filters

Quang, NK Hieu, NT Ha, QP

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Publication Type:: Journal Article
Citation:: IEEE Transactions on Industrial Electronics, 2014, 61 (12), pp. 6574 - 6582
Issue Date:: 2014-12-01

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Field	Value	Language
dc.contributor.author	Quang, NK	en_US
dc.contributor.author	Hieu, NT	en_US
dc.contributor.author	Ha, QP https://orcid.org/0000-0003-0978-1758	en_US
dc.date.issued	2014-12-01	en_US
dc.identifier.citation	IEEE Transactions on Industrial Electronics, 2014, 61 (12), pp. 6574 - 6582	en_US
dc.identifier.issn	0278-0046	en_US
dc.identifier.uri	http://hdl.handle.net/10453/30093
dc.description.abstract	© 2014 IEEE. This paper presents the design and implementation of a field-programmable gate array (FPGA)-based architecture for the speed control of sensorless permanent-magnet synchronous motor (PMSM) drives. For the reduction of computation resources, as well as accuracy improvement in the rotor position estimation, a parallel reduced-order extended Kalman filter (EKF) is proposed in this work. Compared with an EKF, the system order is reduced and the iteration process is greatly simplified, resulting in significant savings of resource utility, while maintaining high estimation performance. The whole control system includes a current-control-and-coordinate-transformation unit, a proportional-integral (PI) speed controller, and other accessory modules, all implemented in a single FPGA chip. A hardware description language is adopted to describe advantageous features of the proposed control system. Moreover, the finite-state-machine method is applied with the purpose to reduce logic elements used in the FPGA chip. The validity of the approach is verified through simulation based on the Modelsim/Simulink cosimulation method. Finally, experimental results are obtained on an FPGA platform with an inverter-fed PMSM to show the feasibility and effectiveness of the proposed system-on-programmable-chip for PMSM drives.	en_US
dc.relation.ispartof	IEEE Transactions on Industrial Electronics	en_US
dc.relation.isbasedon	10.1109/TIE.2014.2320215	en_US
dc.subject.classification	Electrical & Electronic Engineering	en_US
dc.title	FPGA-based sensorless PMSM speed control using reduced-order extended kalman filters	en_US
dc.type	Journal Article
utslib.citation.volume	12	en_US
utslib.citation.volume	61	en_US
utslib.for	0906 Electrical and Electronic Engineering	en_US
utslib.for	08 Information and Computing Sciences	en_US
utslib.for	09 Engineering	en_US
pubs.embargo.period	Not known	en_US
pubs.organisational-group	/University of Technology Sydney
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology
pubs.organisational-group	/University of Technology Sydney/Faculty of Engineering and Information Technology/School of Electrical and Data Engineering
pubs.organisational-group	/University of Technology Sydney/Strength - CBI - Centre for Built Infrastructure
utslib.copyright.status	closed_access
pubs.issue	12	en_US
pubs.publication-status	Published	en_US
pubs.volume	61	en_US

Abstract:

© 2014 IEEE. This paper presents the design and implementation of a field-programmable gate array (FPGA)-based architecture for the speed control of sensorless permanent-magnet synchronous motor (PMSM) drives. For the reduction of computation resources, as well as accuracy improvement in the rotor position estimation, a parallel reduced-order extended Kalman filter (EKF) is proposed in this work. Compared with an EKF, the system order is reduced and the iteration process is greatly simplified, resulting in significant savings of resource utility, while maintaining high estimation performance. The whole control system includes a current-control-and-coordinate-transformation unit, a proportional-integral (PI) speed controller, and other accessory modules, all implemented in a single FPGA chip. A hardware description language is adopted to describe advantageous features of the proposed control system. Moreover, the finite-state-machine method is applied with the purpose to reduce logic elements used in the FPGA chip. The validity of the approach is verified through simulation based on the Modelsim/Simulink cosimulation method. Finally, experimental results are obtained on an FPGA platform with an inverter-fed PMSM to show the feasibility and effectiveness of the proposed system-on-programmable-chip for PMSM drives.

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http://hdl.handle.net/10453/30093