Miniaturized on-chip passive devices for millimetre-wave applications in Bi-CMOS technology
- Publication Type:
- Thesis
- Issue Date:
- 2019
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Recent advances in silicon-based integrated circuits (ICs) have successfully demonstrated promising system-on-chip (SoC) solutions to support micro- and millimeter-wave (mm-wave) applications. As the end of Moore’s Law is approaching, the full potential of active devices is eventually going to be reached. The technical advancement of these emerging technologies can further push through the introduction of alternative equivalent scaling techniques such as the implementation of new design geometries. As the interest in the mm-wave band grows, circuit miniaturization is faced with a unique set of challenges and constraints. In this work, we looked at the growing potential of monolithic integration to design high-performance transceiver system building blocks.
This thesis presents a passive inspired implementation of resonator and bandpass filters designed, and fabricated using IHP 0.13 μm SiGe Bi-CMOS process. Two unique miniaturization design methodologies are presented in this work. In order to fully demonstrate the insight of this approach, a simplified equivalent LC-circuit model is used for theoretical analysis. Using the analyzed results as a guideline along with a full-wave electromagnetic (EM) simulator, two compact bandpass filters (BPFs) are implemented and designed for mm-wave applications.
The first design methodology is a folded-strip-line-based design. The proposed method is based on a planar structure in which neither broadside coupling nor crossover between metals is required. Only a single metal layer is used to implement a compact resonator. To demonstrate its flexibility a BPF is designed. The 1st BPF has one transmission zero at 58 GHz with a peak attenuation of 23 dB. The center frequency of this filter is 27 GHz with an insertion loss of 2.5 dB, while the S₁₁ is better than 10 dB from 26 to 31 GHz. The 2nd BPF has two transmission zeros, and a minimum insertion loss of 3.5 dB is found at 29 GHz. The S₁₁ is better than 10 dB from 26 GHz to 34 GHz. Also, more than 20 dB stop-band attenuation is achieved from DC to 20.5 GHz and from 48 GHz to 67 GHz. The chip sizes of these two BPFs, excluding the pads, are only 0.023 mm² and 0.028 mm², respectively.
The second methodology is designed with ultra-wideband and low insertion loss. The proposed approach uses merely a combination of meander-line structures with metal-insulator-metal (MIM) capacitors. For the 1st BPF, the return loss is better than 10 dB from 13.5 to 32 GHz, which indicates a fractional bandwidth of more than 78%. Also, the minimum insertion loss of 2.3 dB is achieved within the frequency range from 17 GHz to 27 GHz, and the in-band magnitude ripple is less than 0.1 dB. The chip size of this design, excluding the pads, is 0.148 mm². To demonstrate a miniaturized design, a 2nd design example is given. The return loss is better than 10 dB from 17.3 to 35.9 GHz, which indicates a fractional bandwidth of more than 70%. Also, the minimum insertion loss of 2.6 dB is achieved within the frequency range from 21.4 GHz to 27.7 GHz, and the in-band magnitude ripple is less than 0.1 dB. The chip size of the 2nd design, excluding the pads, is only 0.066 mm².
The overall performances of both proposed structures are suitable for miniaturizing design in silicon-based technology. The presented design can be useful to co-design with active devices. As compared to the previously published literature, the presented design in this thesis offer a promising solution in scaling down the physical size of the passive component.
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