A sparse spin qubit array with integrated control electronics

Boter, JM; Dehollain, JP; Van DIjk, JPG; Hensgens, T; Versluis, R; Clarke, JS; Veldhorst, M; Sebastiano, F; Vandersypen, LMK

A sparse spin qubit array with integrated control electronics

Boter, JM Dehollain, JP Van DIjk, JPG Hensgens, T Versluis, R Clarke, JS Veldhorst, M Sebastiano, F Vandersypen, LMK

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Publication Type:: Conference Proceeding
Citation:: Technical Digest - International Electron Devices Meeting, IEDM, 2019, 2019-December
Issue Date:: 2019-12-01

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Field	Value	Language
dc.contributor.author	Boter, JM
dc.contributor.author	Dehollain, JP
dc.contributor.author	Van DIjk, JPG
dc.contributor.author	Hensgens, T
dc.contributor.author	Versluis, R
dc.contributor.author	Clarke, JS
dc.contributor.author	Veldhorst, M
dc.contributor.author	Sebastiano, F
dc.contributor.author	Vandersypen, LMK
dc.date.accessioned	2020-05-02T01:34:17Z
dc.date.available	2020-05-02T01:34:17Z
dc.date.issued	2019-12-01
dc.identifier.citation	Technical Digest - International Electron Devices Meeting, IEDM, 2019, 2019-December
dc.identifier.isbn	9781728140315
dc.identifier.issn	0163-1918
dc.identifier.uri	http://hdl.handle.net/10453/140403
dc.description.abstract	© 2019 IEEE. Current implementations of quantum computers suffer from large numbers of control lines per qubit, becoming unmanageable with system scale up. Here, we discuss a sparse spin-qubit architecture featuring integrated control electronics significantly reducing the off-chip wire count. This quantum-classical hardware integration closes the feasibility gap towards a CMOS quantum computer.
dc.language	en
dc.relation.ispartof	Technical Digest - International Electron Devices Meeting, IEDM
dc.relation.isbasedon	10.1109/IEDM19573.2019.8993570
dc.rights	info:eu-repo/semantics/embargoedAccess
dc.title	A sparse spin qubit array with integrated control electronics
dc.type	Conference Proceeding
utslib.citation.volume	2019-December
pubs.organisational-group	/University of Technology Sydney/Faculty of Science
pubs.organisational-group	/University of Technology Sydney/Strength - QSI - Centre for Quantum Software and Information
pubs.organisational-group	/University of Technology Sydney/Faculty of Science/School of Mathematical and Physical Sciences
pubs.organisational-group	/University of Technology Sydney
utslib.copyright.status	open_access	*
utslib.copyright.embargo	2021-12-31T00:00:00+1000Z
dc.date.updated	2020-05-02T01:34:16Z
pubs.publication-status	Published
pubs.volume	2019-December

Abstract:

© 2019 IEEE. Current implementations of quantum computers suffer from large numbers of control lines per qubit, becoming unmanageable with system scale up. Here, we discuss a sparse spin-qubit architecture featuring integrated control electronics significantly reducing the off-chip wire count. This quantum-classical hardware integration closes the feasibility gap towards a CMOS quantum computer.

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http://hdl.handle.net/10453/140403